From 01fe72d9fcbddd32af0527d7be40e21c7f92d1b0 Mon Sep 17 00:00:00 2001
From: Vern Paxson <vern@corelight.com>
Date: Wed, 4 Dec 2024 15:21:20 -0700
Subject: [PATCH] added type coercion for bit-shifting expressions

---
 auxil/gen-zam | 2 +-
 src/Expr.cc   | 5 ++++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/auxil/gen-zam b/auxil/gen-zam
index 3c17f9797e..0f32b4a05a 160000
--- a/auxil/gen-zam
+++ b/auxil/gen-zam
@@ -1 +1 @@
-Subproject commit 3c17f9797ebab5157d7b08265540cd7f4de15d1f
+Subproject commit 0f32b4a05a7e1772d1a0a9b366ebd7a815e1af39
diff --git a/src/Expr.cc b/src/Expr.cc
index 878002d598..cd1c98ebd3 100644
--- a/src/Expr.cc
+++ b/src/Expr.cc
@@ -1860,8 +1860,11 @@ BitExpr::BitExpr(ExprTag arg_tag, ExprPtr arg_op1, ExprPtr arg_op2)
         if ( IsIntegral(bt1) && bt2 == TYPE_COUNT ) {
             if ( is_vector(op1) || is_vector(op2) )
                 SetType(make_intrusive<VectorType>(base_type(bt1)));
-            else
+            else {
                 SetType(base_type(bt1));
+                if ( bt1 != bt2 )
+                    op2 = make_intrusive<ArithCoerceExpr>(op2, bt1);
+            }
         }
 
         else if ( IsIntegral(bt1) && bt2 == TYPE_INT )